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never stop thinking. data sheet, v1.2, dec. 2002 microcontrollers TC1765 32-bit single-chip microcontroller
edition 2002-12 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2002. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. data sheet, v1.2, dec. 2002 microcontrollers TC1765 32-bit single-chip microcontroller
TC1765 data sheet preliminary revision history: 2002-12 v1.2 previous version: v1.1, 2002-10, v1.0, 2002-05 page subjects (major changes since last revision) changes from v1.1 to v1.2 58 , 59 overshoot conditions (notes 2) and 3) ) for digital supply voltages added 60 class a pins: input low voltage v ilmin (cmos) improved; pull-up/pull-down current spec corrected and completed; 61 class a pins: pull-up/pull-down current spec corrected and completed; 62 note 7) inserted 69 note 3) added to ?sum of i dds ? 80 t 30min corrected 83 package outlines updated (no more ?preliminary? in drawing) changes from v1.0 to v1.1 all in general: data sheet status changed from ?advance information? to ?preliminary? 22 the ssc rxfifo and txfifo are 4-stage fifos (not 8-stage) 61 input hysteresis corrected 62 footnote 10) added 66 footnote 8) : word ?numeric? added 69 missing power supply currents now specified 74 last paragraph modified because of figure 29 correction 75 figure 29 corrected and improved 81 t 55 added (min. value) and corrected (max. value) 82 t 61min and t 62min corrected we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
data sheet 1 v1.2, 2002-12 TC1765 32-bit single-chip microcontroller tricore family preliminary high performance 32-bit tricore cpu with 4-stage pipeline ? 25 ns instruction cycle time at 40 mhz cpu/system clock dual issue super-scalar implementation ? instruction triple issue circular buffer and bit-reverse addressing modes for dsp algorithms flexible multi-master interrupt system very fast interrupt response time hardware controlled context switch for task switch and interrupts 48 kbytes of on-chip sram for data and time critical code 8-channel dma controller for fpi bus transactions built-in calibration support on-chip flexible peripheral interface bus (fpi bus) for interconnections of functional units external bus interface unit (ebu) with dedicated pins used for ? communication with external data memories and peripheral units ? instruction fetches from external burst flash program memories on-chip peripheral units ? general purpose timer array (gpta) with a powerful set of digital signal filtering and timer functionality to realize autonomous and complex i/o management ? multifunctional general purpose timer unit (gptu) with three 32-bit timer/counters ? two asynchronous/synchronous serial channels (asc0, asc1) with baudrate generator, parity, framing and overrun error detection ? two high speed synchronous serial channels (ssc0, ssc1) with programmable data length and shift direction ? twincan module with two interconnected can nodes for high efficiency data handling via fifo buffering and gateway data transfer ? two analog-to-digital converter units (adc0, adc1) with 8-bit, 10-bit, or 12-bit resolution and 24 analog inputs ? watchdog timer and system timer 77 digital general purpose i/o lines and one 24-bit analog port on-chip debug support power management system clock generation unit with pll two derivatives with upward compatible pin configuration ? TC1765n ? TC1765t (with additional 16-bit ocds level 2 trace port) ambient temperature under bias: -40 c to +125 c p-lbga-260 package
TC1765 data sheet 2 v1.2, 2002-12 preliminary ordering information the ordering code for infineon microcontrollers provides an exact reference to the required product. this ordering code identifies: the derivative itself, i.e. its function set, the temperature range, and the package and the type of delivery. the TC1765 is available with the following ordering code: type ordering code package description sak-TC1765n-l40eb q67121-c2326 p-lbga-260 32-bit single-chip microcontroller 40 mhz, -40 c to +125 c sak-TC1765t-l40eb q67121-c2348 p-lbga-260 32-bit single-chip microcontroller 40 mhz, -40 c to +125 c (with ocds2 trace port)
TC1765 data sheet 3 v1.2, 2002-12 preliminary block diagram figure 1 TC1765 block diagram traceport (TC1765t only) 16 asc1 mcb04989 twin can ssc0 gpta 4 ebu (external bus unit) 32 24 data [31:0] address [23:0] port 0 16 port 1 analog input connection an [23:0] 24 osc fpi bus ecout xtal2 xtal1 tp jtag & cerberus scu power- watchdog- reset sys. cntrl. jtag io dmu (data memory unit) 32 kb sram tricore cpu max. 40 mhz trace & ocds interrupt v ss v dd 128 64 pmu (program mem ory unit) 8 kb boot rom 16 kb scratch pad ram 1 kb instruction cache 16 16 ebu control 10 chip select 5 ssc1 asc0 gptu adc0 3 2 2 port 2 16 port 3 16 port 4 port 5 3 2 16 5 dma controller adc1 5 16 stm bcu pll 8 8 ocds control ecin 5 3 f p i b u s 32 16 3 5 control v ddram cpuclk v ddsbram analog power supply 10 10 23 v ddp 5 v ssosc v ddosc 32 3 2 7 3 2 16 16
TC1765 data sheet 4 v1.2, 2002-12 preliminary logic symbol figure 2 TC1765 logic symbol mca04973 alternate functions bypass nmi porst hdrst testmode general control v ssm v ddm adc analog power supply v ssosc v ddosc xtal2 xtal1 o scillator cpuclk tms tdo tdi tck jtag / o cds tp [15:0] brkout brkin ocdse trst (TC1765t only) v ss v dd 10 23 digital circuitry power supply v ddp 5 v ddram v ddsbram TC1765t TC1765n v aref1 v agnd1 v dda1 v ssa1 adc1 analog power supply v aref0 v agnd0 v dda0 v ssa0 adc0 analog power supply an[23:0] adc analog inputs port 0 16-bit port 1 16-bit port 2 16-bit port 4 8-bit port 5 5-bit port 3 16-bit gpta gpta / cfg asc1 ssc1 d[31:0] a[23:0] chip select external bus interface 5 10 control ecin ecout g ptu / asc0 / ssc0 / can / adc0 / adc1
TC1765 data sheet 5 v1.2, 2002-12 preliminary pin configuration figure 3 TC1765 pinning for p-lbga-260 package (top view) mcp05009 an 18 a b c d f g h j k l m n p r t u v e a b c d e f g h j k l m n p r t u v 123456789101112131415161718 123456789101112131415161718 an 4 an 0 an 7 an 2 an 5 an 6 an 3 an 1 an 14 an 15 an 21 an 22 an 9 an 10 an 13 an 12 an 11 an 8 an 16 an 19 an 23 an 20 v agnd1 v aref1 v ssa1 v dda1 v dd ram d30 d31 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 v dd v dd d15 d14 d13 d12 d11 ec in ec out v dd d9 d10 d8 d5 d4 d7 d6 v ddm v ssm d2 d3 d1 d0 rd rd/ wr adv bc0 bc1 bc2 bc3 baa code wait/ in d a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a14 a13 a15 a16 a17 a18 a19 a20 a21 a22 a23 cs0 cs1 cs2 cs3 csemu/ csovl tp.0 tp.1 tp.11 tp.10 tp.8 tp.12 tp.9 tp.3 tp.2 tp.7 tp.13 tp.6 tp.5 tp.4 tp.14 tp.15 ocd se brk out tdo tck cpu clk tdi trst tms brk in test mode po rst nmi xtal 2 xtal 1 hd rst by pass p1.0 p1.4 p1.8 p1.9 p1.7 p1.6 p1.5 p1.3 p1.2 p1.1 p1.15 p1.14 p1.12 p1.11 p1.10 p1.13 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.10 p2.7 p2.8 p2.9 p2.11 p2.12 p2.13 p2.14 p2.15 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 p3.11 p3.12 p3.13 p3.14 p3.15 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 p5.0 p5.1 p5.2 p5.3 p5.4 p0.14 p0.15 p0.12 p0.13 p0.10 p0.11 p0.8 p0.9 p0.6 p0.7 p0.4 p0.5 p0.2 p0.3 p0.0 p0.1 v ss osc v dd osc v dd sbram v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v agnd0 v aref0 v ssa0 v dda0 v dd v dd v dd v dd v dd v ddp v ddp v ddp v ddp v ddp v dd v dd n.c. n.c. the trace port is only available in the TC1765t. an 17
TC1765 data sheet 6 v1.2, 2002-12 preliminary table 1 pin definitions and functions symbol pin in out functions d[31:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 t3 r4 p4 r2 r1 r3 n4 p3 m4 n3 l4 m3 n2 m2 l3 m1 l1 k1 k2 k3 j1 j2 h2 h1 j4 h3 g2 g1 f1 e1 f2 h4 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o ebu data bus lines 1)2) the ebu data bus lines d[31:0] serve as external data bus. data bus line 0 data bus line 1 data bus line 2 data bus line 3 data bus line 4 data bus line 5 data bus line 6 data bus line 7 data bus line 8 data bus line 9 data bus line 10 data bus line 11 data bus line 12 data bus line 13 data bus line 14 data bus line 15 data bus line 16 data bus line 17 data bus line 18 data bus line 19 data bus line 20 data bus line 21 data bus line 22 data bus line 23 data bus line 24 data bus line 25 data bus line 26 data bus line 27 data bus line 28 data bus line 29 data bus line 30 data bus line 31
TC1765 data sheet 7 v1.2, 2002-12 preliminary a[23:0] a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 t5 v4 u5 r6 v5 r7 t6 u6 r8 v6 u7 t7 v8 u14 u8 t8 t9 v14 u9 r9 v13 t11 v10 u10 o o o o o o o o o o o o o o o o o o o o o o o o ebu address bus lines 3)4) the ebu address bus lines a[23:0] serve as address bus. address bus line 0 address bus line 1 address bus line 2 address bus line 3 address bus line 4 address bus line 5 address bus line 6 address bus line 7 address bus line 8 address bus line 9 address bus line 10 address bus line 11 address bus line 12 address bus line 13 address bus line 14 address bus line 15 address bus line 16 address bus line 17 address bus line 18 address bus line 19 address bus line 20 address bus line 21 address bus line 22 address bus line 23 cs0 cs1 cs2 cs3 u12 v12 t10 r10 o o o o chip select lines 3)5) chip select output line 0 chip select output line 1 chip select output line 2 chip select output line 3 csemu / csovl v11 o chip select for emulator region / chip select for emulator overlay memory 3)5) table 1 pin definitions and functions (cont?d) symbol pin in out functions
TC1765 data sheet 8 v1.2, 2002-12 preliminary bc0 bc1 bc2 bc3 rd rd/wr adv wait /ind baa code u2 v1 u3 v2 t1 t2 u1 r5 u4 v3 o o o o o o o i o o ebu control lines 1)5) the ebu control lines are required for controlling external memory or peripheral devices. byte control line 0 byte control line 1 byte control line 2 byte control line 3 read control line write control line address valid output wait input / end of burst input burst address advance output code fetch status output the code signal has the same timing as the chip select signals. table 1 pin definitions and functions (cont?d) symbol pin in out functions
TC1765 data sheet 9 v1.2, 2002-12 preliminary an[23:0] an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 an15 an16 an17 an18 an19 an20 an21 an22 an23 a7 d6 b6 d5 a6 b5 c5 a5 a3 c4 c3 b3 d3 d4 e4 e3 a2 a1 b2 b1 c2 f4 f3 d2 i i i i i i i i i i i i i i i i i i i i i i i i adc analog input port the adc analog input port provides 24 analog input lines for the a/d converters adc0 and adc1. analog input 0 analog input 1 analog input 2 analog input 3 analog input 4 analog input 5 analog input 6 analog input 7 analog input 8 analog input 9 analog input 10 analog input 11 analog input 12 analog input 13 analog input 14 analog input 15 analog input 16 analog input 17 analog input 18 analog input 19 analog input 20 analog input 21 analog input 22 analog input 23 table 1 pin definitions and functions (cont?d) symbol pin in out functions
TC1765 data sheet 10 v1.2, 2002-12 preliminary p0 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.11 p0.12 p0.13 p0.14 p0.15 a10 d7 b8 c7 a11 a12 d8 b9 a13 b10 a14 c9 c10 d10 a15 b11 i/o i/o i i/o i i i/o i i i/o i i/o o i/o o i/o o i/o o i/o i/o i/o i o i o port 0 6) port 0 is a 16-bit bi-directional general purpose i/o port that is also used as input/output for asc0, ssc0, can, gptu, adc0, adc1, and the dma controller. gpt0 gptu i/o line 0 / ad0extin0 adc0 external trigger input 0 gpt1 gptu i/o line 1 ad0extin1 adc0 external trigger input 1 dmreq0a dma request input 0a gpt2 gptu i/o line 2 ad1extin0 adc1 external trigger input 0 dmreq1a dma request input 1a gpt3 gptu i/o line 3 ad1extin1 adc1 external trigger input 1 gpt4 gptu i/o line 4 / ad0emux0 adc0 external multiplexer control 0 gpt5 gptu i/o line 5 ad0emux1 adc0 external multiplexer control 1 gpt6 gptu i/o line 6 ad0emux2 adc0 external multiplexer control 2 rxd0 asc0 receiver input/output txd0 asc0 transmitter output sclk0 ssc0 clock input/output mrst0 ssc0 master receive input / ssc0 slave transmit output mtsr0 ssc0 master transmit output / ssc0 slave receive input rxdcan0 can receiver input 0 txdcan0 can transmitter output 0 rxdcan1 can receiver input 1 txdcan1 can transmitter output 1 table 1 pin definitions and functions (cont?d) symbol pin in out functions
TC1765 data sheet 11 v1.2, 2002-12 preliminary p1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p1.8 p1.9 p1.10 p1.11 p1.12 p1.13 p1.14 p1.15 n18 r16 r15 m17 n16 p15 m18 l18 p16 u16 m16 l16 k17 k18 l15 k16 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 1 6) port 1 is a 16-bit bidirectional general purpose i/o port which also serves as input or output for the gpta. in0 / out0 line of gpta in1 / out1 line of gpta in2 / out2 line of gpta in3 / out3 line of gpta in4 / out4 line of gpta in5 / out5 line of gpta in6 / out6 line of gpta in7 / out7 line of gpta in8 / out8 line of gpta in09 / out9 line of gpta in10 / out10 line of gpta in11 / out11 line of gpta in12 / out12 line of gpta in13 / out13 line of gpta in14 / out14 line of gpta in15 / out15 line of gpta p2 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p2.8 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 j18 t15 n15 j17 h18 j16 t16 m15 j15 h16 g18 h15 g15 g17 g16 f18 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 2 6) port 2 is a 16-bit bidirectional general purpose i/o port which also serves as input or output for the gpta. in16 / out16 line of gpta in17 / out17 line of gpta in18 / out18 line of gpta in19 / out19 line of gpta in20 / out20 line of gpta in21 / out21 line of gpta in22 / out22 line of gpta in23 / out23 line of gpta in24 / out24 line of gpta in25 / out25 line of gpta in26 / out26 line of gpta in27 / out27 line of gpta in28 / out28 line of gpta in29 / out29 line of gpta in30 / out30 line of gpta in31 / out31 line of gpta table 1 pin definitions and functions (cont?d) symbol pin in out functions
TC1765 data sheet 12 v1.2, 2002-12 preliminary p3 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 p3.11 p3.12 p3.13 p3.14 p3.15 f16 f15 e18 e16 e15 e17 d18 d17 c18 c17 b18 a18 c14 d15 b17 b16 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 3 6) port 3 is a 16-bit bidirectional general purpose i/o port which also serves as input or output for the gpta. in32 / out32 line of gpta in33 / out33 line of gpta in34 / out34 line of gpta in35 / out35 line of gpta in36 / out36 line of gpta in37 / out37 line of gpta in38 / out38 line of gpta in39 / out39 line of gpta in40 / out40 line of gpta in41 / out41 line of gpta in42 / out42 line of gpta in43 / out43 line of gpta in44 / out44 line of gpta in45 / out45 line of gpta in46 / out46 line of gpta in47 / out47 line of gpta p4 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 d14 c13 a17 b15 c16 d13 c15 c12 i/o i/o i/o i i/o i i/o i/o i/o i/o i/o port 4 6) port 4 is an 8-bit bidirectional general purpose i/o port which also serves as input/output for the gpta or external request input for the dma controller. during hardware reset the port 4 lines are also used as start-up configuration selection inputs and pll clock selection inputs. in48 / out48 line of gpta in49 / out49 line of gpta / dmreq0b dma request input 0b in50 / out50 line of gpta / dmreq1b dma request input 1b in51 / out51 line of gpta in52 / out52 line of gpta / cfg[0] in53 / out53 line of gpta / cfg[1] in54 / out54 line of gpta / cfg[2] in55 / out55 line of gpta / gpta emergency shut down cfg[2:0]: start-up configuration selection inputs these pins are sampled during power-on reset (porst =0). the configuration inputs define the boot options of the TC1765 after a hardware reset operation. table 1 pin definitions and functions (cont?d) symbol pin in out functions
TC1765 data sheet 13 v1.2, 2002-12 preliminary p5 p5.0 p5.1 p5.2 p5.3 p5.4 d12 b13 b14 c11 a16 i/o i/o i o i i/o i/o i/o port 5 6) port 5 is a 5-bit bidirectional general purpose i/o port which also serves as input or output for asc1 and ssc1. rxd1 asc1 receiver input/output dmreq0c dma request input 0c txd1 asc1 transmitter output dmreq1c dma request input 1c sclk1 ssc1 clock input/output mrst1 ssc1 master receive input / ssc1 slave transmit output mtsr1 ssc1 master transmit output / ssc1 slave receive input tp tp.0 tp.1 tp.2 tp.3 tp.4 tp.5 tp.6 tp.7 tp.8 tp.9 tp.10 tp.11 tp.12 tp.13 tp.14 tp.15 g7 g8 h7 h8 l7 l8 m7 m8 m11 m12 l11 l12 h11 h12 g11 g12 o o o o o o o o o o o o o o o o o ocds-2 trace port 3) tp is the ocds level 2 trace port. the trace port is only available in the TC1765t. the tp outputs are tristated during reset and deep sleep mode. trace output 0 trace output 1 trace output 2 trace output 3 trace output 4 trace output 5 trace output 6 trace output 7 trace output 8 trace output 9 trace output 10 trace output 11 trace output 12 trace output 13 trace output 14 trace output 15 trst 7) r14 i jtag module reset/enable input a low level at this pin resets and disables the jtag module. a high level enables the jtag module. tck 7) t13 i jtag module clock input tdi 8) t14 i jtag module serial data input table 1 pin definitions and functions (cont?d) symbol pin in out functions
TC1765 data sheet 14 v1.2, 2002-12 preliminary tdo r12 o jtag module serial data output 3) tms 8) v15 i jtag module state machine control input ocdse 8) r11 i ocds enable input a low level on this pin during power-on reset (porst =0) enables the on-chip debug support (ocds). in addition, the level of this pin during power-on reset determines the boot configuration. brkin 8) u15 i ocds break input a low level on this pin causes a break in the chip?s execution when the ocds is enabled. in addition, the level of this pin during power-on reset determines the boot configuration. brkout t12 o ocds break output 3) a low level on this pin indicates that a programmable ocds event has occurred. nmi 8) u17 i non-maskable interrupt input a high-to-low transition on this pin causes an nmi-trap request to the cpu. hdrst 8) p18 i/o hardware reset input / reset indication output 6) assertion of this open-drain bidirectional pin causes a synchronous reset of the chip through external circuitry. the internal reset circuitry drives this pin in response to a power-on, hardware, watchdog and power-down wake-up reset for a specific period of time. for a software reset, it is programmable whether this pin is activated or not. porst t17 i power-on reset input a low level on porst causes an asynchronous reset of the entire chip. during power-up of the TC1765, this pin must be held active (low). bypass n17 i pll bypass control input this pin is sampled during power-on reset (porst = 0). if bypass is at high level, direct drive mode operation of the clock circuitry is selected and the pll is bypassed. table 1 pin definitions and functions (cont?d) symbol pin in out functions
TC1765 data sheet 15 v1.2, 2002-12 preliminary xtal1 xtal2 u18 t18 i o oscillator/pll/clock generator input/output pins xtal1 is the input to the oscillator amplifier and input to the internal clock generator. xtal2 is the output of the oscillator amplifier circuit. for clocking the device from an external source, xtal1 is driven with the clock signal while xtal2 is left unconnected. for crystal oscillator operation xtal1 and xtal2 are connected to the crystal with the appropriate recommended oscillator circuitry. ecout p1 o ebu clock output 3) ecin n1 ? ebu clock input the ecin pin is used to latch the data from external components into the ebu. this pin has to be connected to the ecout pin. additional delay elements might be used to adapt to long delays at the address and data lines. cpuclk r13 o cpu clock output 3) general purpose clock output (can be disabled if not used). in addition, the ocds-2 trace output data are synchronous to this clock. test mode 8) v16 i test mode select input for normal operation of the TC1765 this pin should be connected to v dd . v ddosc r18 ? main oscillator power supply (2.5 v) 9) v ssosc r17 ? main oscillator ground v dd j3, p2, t4, v7, u11, u13, l2, f17, d11, v9 ? core and ebu power supply (2.5 v) 9) table 1 pin definitions and functions (cont?d) symbol pin in out functions
TC1765 data sheet 16 v1.2, 2002-12 preliminary v ddp l17, h17, d16, b12, c8 ? port 0 to 5 and dedicated pins power supply (3.3 - 5 v) 10) v ddram g3 ? power supply for pmu memories (2.5 v) 9) v ddsbram p17 ? power supply for dmu memory (2.5 v) 9) used for normal and stand-by operating mode. v ss d9, k4, k15, g9, g10, h9, h10, j7, j8, j9, j10, j11, j12, k7, k8, k9, k10, k11, k12, l9, l10, m9, m10 ? ground table 1 pin definitions and functions (cont?d) symbol pin in out functions
TC1765 data sheet 17 v1.2, 2002-12 preliminary v ddm b4 ? adc analog part power supply (5 v) 10) v ssm a4 ? adc analog part ground for v ddm v dda0 a9 ? adc0 analog part power supply (2.5 v) 9) v ssa0 b7 ? adc0 analog part ground for v dda0 v dda1 g4 ? adc1 analog part power supply (2.5 v) 9) v ssa1 d1 ? adc1 analog part ground for v dda1 v aref0 a8 ? adc0 reference voltage 10) v agnd0 c6 ? adc0 reference ground v aref1 c1 ? adc1 reference voltage 10) v agnd1 e2 ? adc1 reference ground 10) n.c. v17, v18 ? not connected; reserved for future expansions 1) these pins have a drive capability of 600 a when used as outputs. 2) these pins can be connected with internal pull-up devices by setting bit scu_con.ebudpen. 3) these outputs have a drive capability of 600 a. 4) these pins can be connected with internal pull-up devices by setting bit scu_con.ebuapen. 5) these pins can be connected with internal pull-up devices by setting bit scu_con.ebucpen. 6) these pins have a drive capability of 2.4 ma when used as outputs. 7) these pins have an internal pull-down device connected. 8) these pins have an internal pull-up device connected. 9) the voltage on power supply pins marked with 10) has to be raised earlier or at least at the same time (= time window of 1 s) than on power supply pins marked with 9) (details see power supply section on page 54 ). 10) see note 9) . table 1 pin definitions and functions (cont?d) symbol pin in out functions
TC1765 data sheet 18 v1.2, 2002-12 preliminary parallel ports the TC1765 has 77 digital input/output port lines organized into four parallel 16-bit ports (port 0 to port 3), one 8-bit port (port 4), and one 5-bit port (port 5). additionally, 24 analog input port lines are available. the external bus unit (ebu) is provided with dedicated data, address, and control lines. a 16-bit trace port is available only in the TC1765t. the digital parallel ports port 0 to port 5 can be all used as general purpose i/o lines or they can perform input/output functions for the on-chip peripheral units. the on-chip external bus interface unit allows to communicate with external memories, external peripherals, or external debugging devices. an overview on the port-to-peripheral unit assignment is shown in figure 4 . note: for further details on the three pin classes of the TC1765 i/o pins see also table 8 on page 56 ): figure 4 parallel ports of the TC1765 TC1765n TC1765t parallel ports mca04981 port 0 port 1 port 2 port 3 port 4 port 5 gpio alternate functions g ptu / asc0 / ssc0 / can / adc0 / adc1 gpta gpta gpta gpta / cfg asc1 / ssc1 external bus interface tp[15:0] ocds trace port (TC1765t only) address bus a[23:0] data bus d[31:0] an[23:0] control lines
TC1765 data sheet 19 v1.2, 2002-12 preliminary serial interfaces the TC1765 includes five serial peripheral interface units: ? two asynchronous/synchronous serial interfaces (asc0 and asc1) ? two high-speed synchronous serial interfaces (ssc0 and ssc1) ? one twincan interface asynchronous/synchronous serial interfaces figure 5 shows a global view of the functional blocks of the two asynchronous/ synchronous serial interfaces asc0 and asc1. figure 5 general block diagram of the asc interfaces mcb05050 asc0 module (kernel) port 0 control rxd0 txd0 asc1 module (kernel) rxd1 txd1 p0.7 / rxd0 p0.8 / txd0 p5.0 / rxd1 p5.1 / txd1 port 5 control clock control address decoder interrupt control f asc1 eir tbir tir rir clock control address decoder interrupt control f asc0 to dma eir tbir rir tir to dma
TC1765 data sheet 20 v1.2, 2002-12 preliminary each asc module, asc0 and asc1, communicates with the external world via two i/o lines. the rxd line is the receive data input signal (in synchronous mode also output). txd is the transmit output signal. clock control, address decoding, and interrupt service request control are managed outside the asc module kernel. the asynchronous/synchronous serial interfaces provide serial communication between the TC1765 and other microcontrollers, microprocessors, or external peripherals. the asc supports full-duplex asynchronous communication and half-duplex synchronous communication. in synchronous mode, data is transmitted or received synchronous to a shift clock which is generated by the asc internally. in asynchronous mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. parity, framing, and overrun error detection are provided to increase the reliability of data transfers. transmission and reception of data are double-buffered. for multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. testing is supported by a loop-back option. a 13-bit baud rate generator provides the asc with a separate serial clock signal that can be very accurately adjusted by a prescaler implemented as a fractional divider. features: full-duplex asynchronous operating modes ? 8-bit or 9-bit data frames, lsb first ? parity bit generation/checking ? one or two stop bits ? baud rate from 2.5 mbit/s to 0.6 bit/s (@ 40 mhz clock) ? multiprocessor mode for automatic address/data byte detection ? loop-back capability half-duplex 8-bit synchronous operating mode ? baud rate from 5 mbit/s to 406.9 bit/s (@ 40 mhz clock) double buffered transmitter/receiver interrupt generation ? on a transmitter buffer empty condition ? on a transmit last bit of a frame condition ? on a receiver buffer full condition ? on an error condition (frame, parity, overrun error)
TC1765 data sheet 21 v1.2, 2002-12 preliminary high-speed synchronous serial interfaces figure 6 shows a global view of the functional blocks of the two high-speed synchronous serial interfaces ssc0 and ssc1. figure 6 general block diagram of the ssc interfaces each of the ssc modules has three i/o lines, located at port 0 and port 5. each of the ssc modules is further supplied by separate clock control, interrupt control, address decoding, and port control logic. the ssc supports full-duplex and half-duplex serial synchronous communication up to 20 mbit/s (@ 40 mhz module clock) with receive and transmit fifo support. the serial clock signal can be generated by the ssc itself (master mode) or can be received from an external master (slave mode). data width, shift direction, clock polarity, and phase are programmable. this allows communication with spi-compatible devices. transmission mcb05051 clock control address decoder interrupt control f ssc0 ssc0 module (kernel) clock control address decoder interrupt control f ssc1 ssc1 module (kernel) rxd txd master rxd txd slave slave master sclk rxd txd master rxd txd slave slave master sclk port 0 control p0.10 / mrst0 p0.11 / mtsr0 p0.9 / sclk0 port 5 control p5.4 / mtsr1 p5.3 / mrst1 p5.2 / sclk1 eir rir to dma eir tir rir to dma tir
TC1765 data sheet 22 v1.2, 2002-12 preliminary and reception of data are double-buffered. a 16-bit baud rate generator provides the ssc with a separate serial clock signal. features: master and slave mode operation ? full-duplex or half-duplex operation flexible data format ? programmable number of data bits: 2-bit to 16 bit ? programmable shift direction: lsb or msb shift first ? programmable clock polarity: idle low or high state for the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock baud rate generation from 20 mbit/s to 305.18 bit/s (@ 40 mhz module clock) interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, phase, baud rate, transmit error) three-pin interface ? flexible ssc pin configuration 4-stage receive fifo (rxfifo) and 4-stage transmit fifo (txfifo) ? independent control of rxfifo and txfifo ? 2 to 16 bit fifo data width ? programmable receive/transmit interrupt trigger level ? receive and transmit fifo filling level indication ? overrun error generation ? underflow error generation
TC1765 data sheet 23 v1.2, 2002-12 preliminary twincan interface figure 7 shows a global view of the functional blocks of the twincan module. figure 7 general block diagram of the twincan module the twincan module has four i/o lines located at port 0. the twincan module is further supplied by a clock control, interrupt control, address decoding, and port control logic. the twincan module contains two full-can nodes operating independently or exchanging data and remote frames via a gateway function. transmission and reception of can frames are handled in accordance to can specification v2.0 part b (active). each of the two full-can nodes can receive and transmit standard frames with 11-bit identifiers as well as with extended frames with 29-bit identifiers. both can nodes share the twincan module?s resources to optimize the can bus traffic handling and to minimize the cpu load. the flexible combination of full-can functionality and the fifo architecture reduces the efforts to fulfill the real-time requirements of complex embedded control applications. improved can bus monitoring functionality as well as the increased number of message objects permit precise and convenient can bus traffic handling. depending on the application, each of the thirty-two message objects can be individually assigned to one of the two can nodes. gateway functionality allows automatic data exchange between two separate can bus systems, which decreases cpu load and improves the real time behavior of the entire system. twincan module kernel message buffers mcb05059 clock control address decoder interrupt control sr1 sr2 f can sr3 sr0 port control p0.13 / txdcan0 p0.12 / rxdcan0 sr7 sr6 sr5 p0.15 / txdcan1 p0.14 / rxdcan1 bitstream processor sr4 txdc0 rxdc0 txdc1 rxdc1 error h andling control timing control interrupt control
TC1765 data sheet 24 v1.2, 2002-12 preliminary the bit timings for both can nodes are derived from the peripheral clock ( f can ) and are programmable up to a data rate of 1 mbit/s. a pair of receive and transmit pins connect each can node to a bus transceiver. features: can functionality conforms to can specification v2.0 b active. dedicated control registers are provided for each can node. a data transfer rate up to 1 mbit/s is supported. flexible and powerful message transfer control and error handling capabilities are implemented. full-can functionality: 32 message objects can be individually ? assigned to one of the two can nodes ? configured as transmit or receive object ? participate in a 2, 4, 8, 16 or 32 message buffer with fifo algorithm ? set up to handle frames with 11-bit or 29-bit identifiers ? provided with programmable acceptance mask register for filtering ? monitored via a frame counter ? configured to remote monitoring mode up to eight individually programmable interrupt nodes can be used. can analyzer mode for bus monitoring is implemented.
TC1765 data sheet 25 v1.2, 2002-12 preliminary timer units the TC1765 includes two timer units: ? general purpose timer unit (gptu) ? general purpose timer array (gpta) general purpose timer unit figure 8 shows a global view of the general purpose timer unit (gptu) module. figure 8 general block diagram of the gptu interface the gptu consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. the gptu communicates with the external world via eight inputs and eight outputs located at port 0. the i/o has three timers (t0, t1, and t2) can operate independently from each other, or can be combined. general features: all timers are 32-bit precision timers with a maximum input frequency of f gptu . events generated in t0 or t1 can be used to trigger actions in t2. timer overflow or underflow in t2 can be used to clock either t0 or t1. t0 and t1 can be concatenated to form one 64-bit timer. mcb05052 clock control address decoder interrupt control sr1 sr2 f gptu sr3 sr0 gptu module (kernel) port control p0.1 / g pt1 sr7 sr6 sr5 sr4 in 1 in 2 in 3 in 0 in 7 in 6 in 5 in 4 out0 out1 out2 out3 out4 out5 out6 out7 io 1 not connected io 7 io 0 p0.0 / g pt0 io 2 p0.2 / g pt2 io 3 p0.3 / g pt3 p0.4 / g pt4 io 4 io 5 p0.5 / g pt5 io 6 p0.6 / g pt6
TC1765 data sheet 26 v1.2, 2002-12 preliminary features of t0 and t1: each timer has a dedicated 32-bit reload register with automatic reload on overflow. timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers. overflow signals can be selected to generate service requests, pin output signals, and t2 trigger events. two input pins can define a count option. features of t2: count up or down is selectable operating modes: ?timer ? counter ? quadrature counter (incremental/phase encoded counter interface) options: ? external start/stop, one-shot operation, timer clear on external event ? count direction control through software or an external event ? two 32-bit reload/capture registers reload modes: ? reload on overflow or underflow ? reload on external event: positive transition, negative transition, or both transitions capture modes: ? capture on external event: positive transition, negative transition, or both transitions ? capture and clear timer on external event: positive transition, negative transition, or both transitions can be split into two 16-bit counter/timers timer count, reload, capture, and trigger functions can be assigned to input pins. t0 and t1 overflow events can also be assigned to these functions. overflow and underflow signals can be used to trigger t0 and/or t1 and to toggle output pins. t2 events are freely assignable to the service request nodes.
TC1765 data sheet 27 v1.2, 2002-12 preliminary general purpose timer array figure 9 shows a global block diagram of the general purpose timer array (gpta). figure 9 gpta module block diagram the gpta module has 56 input signals and 56 output signals which are connected with 56 port 1, port 2, port 3, and port 4 pins. the general purpose timer array (gpta) provides important digital signal filtering and timer support whose combination enables autonomous and complex functionalities. this architecture allows easy implementation and easy validation of any kind of timer functions. mcb05053 port control io 54 io 55 p4.0 p4.1 p4.6 p4.7 gpta module kernel clock generation unit filter & prescaler cells phase discriminator logic duty cycle measurement digital phase locked loop interrupt control unit io sharing unit with emergency shut-off signal generation unit global timers global timer cells local timer cells out54 out55 io 48 io 49 io 46 io 47 p3.0 p3.1 p3.14 p3.15 io 32 io 33 io 30 io 31 p2.0 p2.1 p2.14 p2.15 io 16 io 17 io 14 io 15 p1.0 p1.1 p1.14 p1.15 io 0 io 1 in0 in1 out0 out1 in 55 in 54 as0 as1 as55 clock control address decoder a/d converter ptin01 ptin10 f gpta ptin11 ptin00 interrupt control sr01 sr52 sr53 sr00 to dma ltc54 gtc30 as54
TC1765 data sheet 28 v1.2, 2002-12 preliminary the general purpose timer array (gpta) provides a set of hardware modules required for high speed digital signal processing: filter and prescaler cells (fpc) support input noise filtering and prescaler operation. phase discrimination logic units (pdl) decode the direction information output by a rotation tracking system. duty cycle measurement cells (dcm) provide pulse width measurement capabilities. a digital phase locked loop unit (pll) generates a programmable number of gpta module clock ticks during an input signal?s period. global timer units (gt) driven by various clock sources are implemented to operate as a time base for the associated ?global timer cells?. global timer cells (gtc) can be programmed to capture the contents of a global timer on an event that occurred at an external port pin or at an internal fpc output. a gtc may be also used to control an external port pin with the result of an internal compare operation. gtcs can be logically concatenated to provide a common external port pin with a complex signal waveform. local timer cells (ltc) operating in timer, capture, or compare mode may be also logically tied together to drive a common external port pin with a complex signal waveform. ltcs ? enabled in timer mode or capture mode ? can be clocked or triggered by ? a prescaled gpta module clock, ? an fpc, pdl, dcm, pll, or gtc output signal line, ? an external port pin. some input lines driven by processor i/o pads may be shared by a ltc and a gtc cell to trigger their programmed operation simultaneously. the following list summarizes all blocks supported: clock generation unit: filter and prescaler cell (fpc): ? six independent units ? three operating modes (prescaler, delayed debounce filter, immediate debounce filter) ? f gpta down-scaling capability ? f gpta /2 maximum input signal frequency in filter mode phase discriminator logic (pdl): ? two independent units ? two operating modes (2 and 3 sensor signals) ? f gpta /4 maximum input signal frequency in 2-sensor mode, f gpta /6 maximum input signal frequency in 3-sensor mode duty cycle measurement (dcm): ? four independent units ? 0 - 100% margin and time-out handling
TC1765 data sheet 29 v1.2, 2002-12 preliminary ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency digital phase locked loop (pll): ? one unit ? arbitrary multiplication factor between 1 and 65535 ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency signal generation unit: global timers (gt): ? two independent units ? two operating modes (free running timer and reload timer) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency global timer cell (gtc): ? 32 independent units ? two operating modes (capture, compare and capture after compare) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency local timer cell (ltc): ? 64 independent units ? three operating modes (timer, capture and compare) ? 16-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency interrupt control unit: 111 interrupt sources generating 54 service requests i/o sharing unit: interconnecting input and output lines from fpc, gtc, ltc and ports emergency function
TC1765 data sheet 30 v1.2, 2002-12 preliminary analog-to-digital converters the two on-chip adc modules of the TC1765 are analog to digital converters with 8-bit, 10-bit or 12-bit resolution including sample & hold functionality. the a/d converters operate by the method of the successive approximation. a multiplexer selects between up to 16 analog input channels for each adc module. the 24 analog inputs are switched to the analog input channels of the adc modules by a fixed scheme. conversion requests are generated either under software control or by hardware (gpta). an automatic self-calibration adjusts the adc modules to changing temperatures or process variations. features: 8-bit, 10-bit, 12-bit a/d conversion successive approximation conversion method fast conversion times: e.g. 10-bit conversion (without sample time): 2.05 s total unadjusted error (tue) of 2 lsb @ 10-bit resolution integrated sample and hold functionality 24 analog input pins / 16 analog input channels of each adc module fix assignment of 24 analog input pins to the 32 adc0/adc1 input channels dedicated control and status registers for each analog channel flexible conversion request mechanisms selectable reference voltages for each channel programmable sample and conversion timing schemes limit checking flexible adc module service request control unit synchronization of the two on-chip a/d converters automatic control of an external analog input multiplexer for adc0 equidistant samples initiated by timer two trigger inputs, connected with the general purpose timer array (gpta) two external trigger input pins of each adc for generating conversion requests power reduction and clock control feature figure 10 shows a global view of the adc module kernel with the module specific interface connections. the adc modules communicate with the external world via five (adc0) or two (adc0) digital i/o lines and sixteen analog inputs. clock control, address decoding, digital i/o port control, and service request generation is managed outside the adc module kernel. the end of a conversion is indicated for each channel n (n = 0-15) by a pulse on the output signals srchn. these signals can be used to trigger a dma transfer to read the conversion result automatically. two trigger inputs and a synchronization bridge are used for internal control purposes.
TC1765 data sheet 31 v1.2, 2002-12 preliminary figure 10 general block diagram of the adc interface mcb05054 clock control address decoder f adc gpta ptin00 sr [3:0] ptin01 adc0 module kernel synchronization bridge adc1 module kernel ptin10 ptin11 port 0 control p0.0 / ad0extin0 p0.1 / ad0extin1 p0.4 / ad0emux0 p0.5 / ad0emux1 p0.6 / ad0emux2 an0 an1 an22 an23 ain15 ain0 ain1 ain13 ain15 port 0 control p0.2 / ad1extin0 p0.3 / ad1extin1 analog pad to adc0/adc1 input channel connection v agnd1 v ssa1 v dda1 v ddm1 v aref1 v ssm1 v agnd1 v ssa1 v dda1 v ddm1 v aref1 v ssm1 interrupt control srch[15:0] to dma address decoder sr[3:0] interrupt control srch[15:0] to dma ain14 ain1 ain0
TC1765 data sheet 32 v1.2, 2002-12 preliminary on-chip memories the memory system of the TC1765 provides the following memories: program memory unit (pmu) with ? 8 kbytes boot rom (brom) ? 16 kbytes code scratch-pad ram (spram) ? 1 kbyte instruction cache (icache) data memory unit (dmu) with ? 32 kbytes data memory (sram) ? can be used for standby operation during power-down states using a separate power supply
TC1765 data sheet 33 v1.2, 2002-12 preliminary address map table 2 defines the segment oriented address blocks of the TC1765 with its address range, size, and pmu/dmu access view. table 3 shows the block address map of segment 15 which includes the on-chip peripheral units. table 2 TC1765 block address map seg- ment address range size description dmu acc. pmu acc. 1) 0 - 7 0000 0000 h - 7fff ffff h 2 gb reserved ? ? 8 8000 0000 h - 8fff ffff h 256 mb reserved via fpi pmu local cached 9 9000 0000 h - 9fff ffff h 256 mb reserved dmu local via fpi 10 a000 0000 h - afff ffff h 256 mb external memory space via fpi via ebu or fpi 11 b000 0000 h - bdff ffff h 224 mb external memory space mappable into segment 10 via fpi via ebu or fpi non-cached be00 0000 h - beff ffff h 16 mb external emulator space via fpi bf00 0000 h - bfff dfff h -16 mb reserved pmu local bfff e000 h - bfff ffff h 8 kb boot rom 4 kbytes general purpose 4 kbytes factory test support 12 c000 0000 h - c000 3fff h 16 kb local code scratch-pad ram (spram) via fpi pmu local c000 4000 h - c7ff feff h ?reserved c7ff ff00 h - c7ff ffff h 256 b pmu control registers c800 0000 h - cfff ffff h ?reserved
TC1765 data sheet 34 v1.2, 2002-12 preliminary 13 d000 0000 h - d000 7fff h 32 kb local data memory (sram) dmu local via fpi non-cached d000 8000 h - d7ff feff h ?reserved d7ff ff00 h - d7ff ffff h 256 b dmu registers d800 0000 h - dfff ffff h 256 mb reserved 14 e000 0000 h - efff ffff h 256 mb external peripheral and data memory space via fpi not possi- ble 15 f000 0000 h - f000 3bff h -16 kb on-chip peripherals & ports via fpi not possi- ble non-cached f000 3c00 h - f000 3dff h 512 b dma registers f000 3e00 h - f00f ffff h ?reserved f010 0000 h - f010 0bff h 12 256 b can module f010 0c00 h - fffe feff h ?reserved fffe ff00 h - fffe ffff h 256 b cpu slave interface registers (cps) ffff 0000 h - ffff ffff h 64 kb core sfrs + gprs 1) the pmu can access external memory directly (?via ebu?, only instruction accesses) or via the fpi bus (?via fpi?). if both paths are possible as defined in this column, selection is done via scu_con.extif. table 2 TC1765 block address map (cont?d) seg- ment address range size description dmu acc. pmu acc. 1)
TC1765 data sheet 35 v1.2, 2002-12 preliminary table 3 block address map of segment 15 symbol description address range size scu system control unit f000 0000 h - f000 00ff h 256 bytes ? reserved f000 0100 h - f000 01ff h ? bcu bus control unit f000 0200 h - f000 02ff h 256 bytes stm system timer f000 0300 h - f000 03ff h 256 bytes ocds on-chip debug support f000 0400 h - f000 04ff h 256 bytes ebu external bus unit f000 0500 h - f000 05ff h 256 bytes ? reserved f000 0600 h - f000 06ff h ? gptu general purpose timer unit f000 0700 h - f000 07ff h 256 bytes asc0 async./sync. serial interface 0 f000 0800 h - f000 08ff h 256 bytes asc1 async./sync. serial interface 1 f000 0900 h - f000 09ff h 256 bytes ssc0 high-speed synchronous serial interface 0 f000 0a00 h - f000-0aff h 256 bytes ssc1 high-speed synchronous serial interface 1 f000 0b00 h - f000-0bff h 256 bytes ? reserved f000 0c00 h - f000 17ff h ? gpta general purpose timer array f000 1800 h - f000 1fff h 8 256 bytes ? reserved f000 2000 h - f000 21ff h ? adc0 analog-to-digital converter 0 f000 2200 h - f000 23ff h 2 256 bytes adc1 analog-to-digital converter 1 f000 2400 h - f000 25ff h 2 256 bytes ? reserved f000 2600 h - f000 27ff h ? p0 port 0 f000 2800 h - f000 28ff h 256 bytes p1 port 1 f000 2900 h - f000 29ff h 256 bytes p2 port 2 f000 2a00 h - f000 2aff h 256 bytes p3 port 3 f000 2b00 h - f000 2bff h 256 bytes p4 port 4 f000 2c00 h - f000 2cff h 256 bytes p5 port 5 f000 2d00 h - f000 2dff h 256 bytes ? reserved f000 2e00 h - f000 3bff h ? dma dma controller f000 3c00 h - f000 3dff h 2 256 bytes ? reserved f000 3e00 h - f00f ffff h ? can 1) controller area network module f010 0000 h - f010 0bff h 12 256 bytes
TC1765 data sheet 36 v1.2, 2002-12 preliminary ? reserved f010 0c00 h - fffe feff h ? cpu slave interface registers (cps) fffe ff00 h - fffe ffff h 256 bytes reserved ffff 0000 h - ffff bfff h ? memory protection registers ffff c000 h - ffff efff h 12 kbytes reserved ffff f000 h - ffff fcff h ? core debug registers (ocds) ffff fd00 h - ffff fdff h 256 bytes core special function registers (csfrs) ffff fe00 h - ffff feff h 256 bytes general purpose registers (gprs) ffff ff00 h - ffff ffff h 256 bytes 1) access to unused address regions within this peripheral unit don?t generate a bus error. table 3 block address map of segment 15 (cont?d) symbol description address range size
TC1765 data sheet 37 v1.2, 2002-12 preliminary memory protection system the TC1765 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. the memory protection system controls the position and range of addressable segments in memory. it also controls the kinds of read and write operations allowed within addressable memory segments. any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate trap service routine (tsr) to handle the error. thus, the memory protection system protects critical system functions against both software and hardware errors. the memory protection hardware can also generate signals to the debug unit to facilitate tracing illegal memory accesses. there are two memory protection register sets in the TC1765, numbered 0 and 1, which specify memory protection ranges and permissions for code and data. the psw.prs bit field determines which of these is the set currently in use by the cpu. because the TC1765 uses a harvard-style memory architecture, each memory protection register set is broken down into a data protection register set and a code protection register set. each data protection register set can specify up to four address ranges to receive particular protection modes. each code protection register set can specify up to two address ranges to receive particular protection modes. each of the data protection register sets and code protection register sets determines the range and protection modes for a separate memory area. each contains register pairs which determine the address range (the data segment protection registers and code segment protection registers) and one register (data protection mode register) which determines the memory access modes which apply to the specified range.
TC1765 data sheet 38 v1.2, 2002-12 preliminary on-chip fpi bus the fpi bus interconnects the functional units of the TC1765, such as the cpu and on- chip peripheral components. the fpi bus also interconnects the TC1765 to external components by way of the external bus controller unit (ebu). the fpi bus is designed to be quick to acquire by on-chip functional units, and quick to transfer data. the low setup overhead of the fpi bus access protocol guarantees fast fpi bus acquisition, which is required for time-critical applications. the fpi bus is designed to sustain high transfer rates. for example, a peak transfer rate of up to 160 mbyte/s can be achieved with a 40 mhz bus clock and 32-bit data bus. multiple data transfers per bus arbitration cycle allow the fpi bus to operate at close to its peak bandwidth. features: supports multiple bus masters supports demultiplexed address/data operation address and data buses are 32 bits wide data transfer types include 8-, 16-, and 32-bit sizes single- and multiple-data transfers per bus acquisition cycle designed to minimize emi and power consumption
TC1765 data sheet 39 v1.2, 2002-12 preliminary external bus unit the external bus unit (ebu) of the TC1765 is the interface between external memories and peripheral units and the internal memories and peripheral units. the basic structure of the ebu is shown in figure 11 . figure 11 ebu structure and interfaces the ebu consists of two parts and is used for the following two operations: fbu (fpi bus unit): ? communication with external memories or peripheral units via the fpi bus ? non-burst instruction fetches bifu (burst instruction fetch unit): ? instruction fetches from the pmu to external burst flash program memories with 16-bit and 32-bit data width the ebu controls all transactions required for these two operations and in particular handles the arbitration between these two tasks. the types of external devices/bus modes controlled by the fbu are: ? intel style peripherals (separate rd and wr signals) ? motorola style peripherals (oe and r/w ) ?roms, eproms ? static rams ? peripherals with demultiplexed a/d bus ? burst mode flash memories ? 8-, 16- and 32-bit data bus width mca04983 tricore cpu pmu with on-chip progam memory dmu with on-chip data memory ebu control lines chip select lines a[23:0] d[31:0] fpi bus burst mode instruction fetches to peripheral units and dma 5 ecout ecin bifu fbu 10
TC1765 data sheet 40 v1.2, 2002-12 preliminary dma controller the direct memory access (dma) controller executes dma transactions from a source address location to a destination address location, without intervention of the cpu. one dma transaction is controlled by one dma channel. each of the two blocks in the dma controller, block 0 and block 1 (see figure 12 ), provides four dma channels with sixteen dma request inputs. the request assignment unit in each sub-block assigns one dma request input to each dma channel. the control unit includes a third request unit dedicated especially for request control through i/o pins. this unit connects two of eight request inputs with two request outputs which can be then wired externally of the dma controller module to the request inputs of the two dma controller blocks. request assignment unit 2 evaluates pulses or levels by its edge detect and level select logic. features: 8 independent dma channels (4 per dma block) ? 4 dma selectable request inputs per dma channel ? fixed priority of dma channels within a dma block ? software and hardware dma request generation support of fpi bus to fpi bus dma transactions individually programmable operation modes for each dma channel ? single mode: stops and disables dma channel after a predefined number of dma transfers ? continuous mode: dma channel remains enabled after a predefined number of dma transfers; dma transaction can be repeated full 32-bit addressing capability of each dma channel ? 4 gbyte address range ? source and destination transfer individually programmable in steps from 0 to 255 bytes ? support of circular buffer addressing mode programmable data width of a dma transaction: 8-bit, 16-bit, or 32-bit register set for each dma channel ? source and destination start address register ? source and destination end address register ? channel control and status register ? offset and transfer count register bus bandwidth allocation flexible interrupt generation figure 12 shows the TC1765 specific implementation details and interconnections of the dma module. the dma module is further supplied by a separate clock control, address decoding, interrupt control, port control logic.
TC1765 data sheet 41 v1.2, 2002-12 preliminary figure 12 dma module block diagram with interconnections mcb04965 clock control address decoder interrupt control sr1 sr6 sr0 control unit sr7 16 16 sub-block 0 request assign. unit 0 dma channels 00-03 sub-block 1 request assign. unit 1 dma channels 10-13 4 4 request assign. unit 2 dma controller p0.1 / dmreq0a p4.1 / dmreq0b p5.0 / dmreq0c gpta3 (gtc30) asc0 asc1 ssc0 ssc1 adc0 adc1 gpta3 (ltc54) p0.2 / dmreq1a p4.2 / dmreq1b p5.1 / dmreq1c reqo0 reqo1 dma request wiring matrix f dma
TC1765 data sheet 42 v1.2, 2002-12 preliminary system timer the TC1765?s system timer (stm) is designed for global system timing applications requiring both high precision and long range. the stm has the following features: free-running 56-bit counter all 56 bits can be read synchronously different 32-bit portions of the 56-bit counter can be read synchronously driven by clock f stm (identical to the system clock f sys ) counting starts automatically after a reset operation (except a hardware reset) the stm is an upward counter, running with the system clock frequency ( f stm = f sys ). it is enabled per default after reset, and immediately starts counting up. other than via reset, it is no possible to affect the contents of the timer during normal operation of the application, it can only be read, but not written to. depending on the implementation of the clock control of the stm, the timer can optionally be disabled or suspended for power-saving and debugging purposes via a clock control register. the maximum clock period is 2 56 1 / f stm . at f stm = 40 mhz, for example, the stm counts 57.1 years before overflowing. thus, it is capable of continuously timing the entire expected product life-time of a system without overflowing. figure 13 block diagram of the system timer module stm module 00 h cap tim6 tim5 tim4 tim3 tim2 tim1 tim0 00 h 55 47 39 31 23 15 7 56-bit system timer address decoder clock control enable / disable porst f stm mca04795
TC1765 data sheet 43 v1.2, 2002-12 preliminary watchdog timer the watchdog timer (wdt) provides a highly reliable and secure way to detect and recover from software or hardware failure. the wdt helps to abort an accidental malfunction of the TC1765 in a user-specified time period. when enabled, the wdt will cause the TC1765 system to be reset if the wdt is not serviced within a user- programmable time period. the cpu must service the wdt within this time interval to prevent the wdt from causing a TC1765 system reset. hence, routine service of the wdt confirms that the system is functioning properly. in addition to this standard ?watchdog? function, the wdt incorporates the endinit feature and monitors its modifications. a system-wide line is connected to the endinit bit implemented in a wdt control register, serving as an additional write-protection for critical registers (besides supervisor mode protection). a further enhancement in the TC1765?s watchdog timer is its reset prewarning operation. instead of immediately resetting the device on the detection of an error, as known from standard watchdogs, the wdt first issues an non-maskable interrupt (nmi) to the cpu before finally resetting the device at a specified time period later. this gives the cpu a chance to save system state to memory for later examination of the cause of the malfunction, an important aid in debugging. features: 16-bit watchdog counter selectable input frequency: f sys /256 or f sys /16384 16-bit user-definable reload value for normal watchdog operation, fixed reload value for time-out and prewarning modes incorporation of the endinit bit and monitoring of its modifications sophisticated password access mechanism with fixed and user-definable password fields proper access always requires two write accesses. the time between the two accesses is monitored by the wdt and limited. access error detection: invalid password (during first access) or invalid guard bits (during second access) trigger the watchdog reset generation. overflow error detection: an overflow of the counter triggers the watchdog reset generation. watchdog function can be disabled; access protection and endinit monitor function remain enabled. double reset detection: if a watchdog induced reset occurs twice without a proper access to its control register in between, a severe system malfunction is assumed and the TC1765 is held in reset until a power-on reset. this prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed.
TC1765 data sheet 44 v1.2, 2002-12 preliminary important debugging support is provided through the reset prewarning operation by first issuing an nmi to the cpu before finally resetting the device after a certain period of time. system control unit the system control unit (scu) of the TC1765 handles the system control tasks. all these system functions are tightly coupled, thus, they are conveniently handled by one unit, the scu. the system tasks of the scu are: reset control ? generation of all internal reset signals ? generation of external hdrst reset signal pll control ? pll_clc clock control register power management control ? enabling of several power-down modes ? control of the pll in power-down modes watchdog timer trace control and trace status indication pull-up/pull-down i/o control device identification
TC1765 data sheet 45 v1.2, 2002-12 preliminary interrupt system an interrupt request is serviced by the cpu. interrupt requests are also called ?service requests? because they are serviced by a ?service provider?, the cpu. each peripheral unit in the TC1765 typically generates service requests. additionally, the bus control unit, the debug unit, the dma controller, and even the cpu itself can generate service requests. several peripheral units are able to generate in parallel to a service request dma requests to the dma controller. as shown in figure 14 , each TC1765 unit that can generate service requests is connected to one or multiple service request nodes (srn). each srn contains a service request control register mod_srcx, where ?mod? is the identifier of the service requesting unit and ?x? an optional index. the interrupt arbitration bus connects the srns with the interrupt control unit, which handles interrupt arbitration among competing interrupt service requests. units which can generate service requests are: ? general purpose timer unit (gptu) with 8 srns ? general purpose timer array (gpta) with 54 srns ? two high-speed synchronous serial interfaces (ssc0/ssc1) with 3 srns each ? two asynchronous/synchronous serial interfaces (asc0/asc1) with 4 srns each ? twincan controller with 8 srns ? two analog/digital converters (adc0/adc1) with 4 srns each ? bus control unit (bcu) with 1 srn ? dma controller processor (dma) with 8 srns ? central processing unit (cpu) with 4 srns ? debug unit (ocds) with 1 srn ? central processing unit (cpu) with 4 srns (software activated) external interrupt inputs in TC1765 are available using the input pins connected to the general purpose timer unit (gptu). each of the seven gptu i/o pins can be used as an external interrupt input, using the service request nodes of the gptu module. additionally, such an external interrupt input can also trigger a timer function.
TC1765 data sheet 46 v1.2, 2002-12 preliminary figure 14 block diagram of the TC1765 interrupt system mcb04993 54 srns 8 srns 8 gptu 54 gpta 3 srns 3 ssc0 3 srns 3 ssc1 4 srns 4 asc0 4 srns 4 asc1 8 srns 8 can 8 srns 8 dma 4 srns 4 adc0 4 srns 4 adc1 1 1 srn bcu service request nodes service requestors 8 54 3 3 4 4 8 8 4 4 1 interrupt arbitration bus 1 debug unit 4 4 srns 4 int. req. pipn cpu ccpn int. ack. software interrupts 1 interrupt control unit icu dma request bus 2 2 2 2 6 6 1 srn 1
TC1765 data sheet 47 v1.2, 2002-12 preliminary boot options the TC1765 booting schemes provides a number of different boot options for the start of code execution. table 4 shows the boot options available in the TC1765. table 4 TC1765 boot selections ocdse brkin cfg[2:0] type of boot boot source pc start value 11000 b start from boot rom entry point 1 boot rom bfff fffc h 001 b start from boot rom entry point 2 010 b start from boot rom entry point 3 011 b start from boot rom entry point 4 100 b external memory as master directly pmu - ebu external memory a000 0000 h 101 b external memory via pmu - fpi bus - ebu 110 b reserved; don?t use these combinations. 111 b 01100 b or 101 b go to halt with ebu enabled as master ?? all other combina- tions go to halt with ebu disabled 0 0 ? go to external emulator space ? be00 0000 h 1 0 ? tri-state chip (deep sleep) ??
TC1765 data sheet 48 v1.2, 2002-12 preliminary power management system the TC1765 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. there are four power management modes: run mode idle mode sleep mode deep sleep mode table 5 describes the features of the power management modes. table 5 power management mode summary mode description run the system is fully operational. all clocks and peripherals are enabled, as determined by software. idle the cpu clock is disabled, waiting for a condition to return it to run mode. idle mode can be entered by software when the processor has no active tasks to perform. all peripherals remain powered and clocked. processor memory is accessible to peripherals. a reset, watchdog timer event, a falling edge on the nmi pin, or any enabled interrupt event will return the system to run mode. sleep the system clock continues to be distributed only to those peripherals programmed to operate in sleep mode. interrupts from operating peripherals, the watchdog timer, a falling edge on the nmi pin, or a reset event will return the system to run mode. entering this state requires an orderly shut-down controlled by the power management state machine. deep sleep the system clock is shut off; only an external signal will restart the system. entering this state requires an orderly shut-down controlled by the power management state machine (pmsm).
TC1765 data sheet 49 v1.2, 2002-12 preliminary on-chip debug support the on-chip debug support (ocds) of the TC1765 consists of four building blocks: ocds module in the tricore cpu ? on-chip breakpoint hardware ? support of an external break signal trace module ? outputs 16 bits each f sys system clock cycle at tp[15:0] with pipeline status information, pc bus information, and breakpoint qualification information dma controller trace ? indication of address counter updates debugger interface cerberus ? provided for debug purposes of emulation tool vendors ? accessible through a jtag standard interface with dedicated jtag port pins figure 15 shows a basic block diagram of the building blocks. . figure 15 ocds basic block diagram scu trace control & status mcb04995 cerberus & jtag trst tck tms tdi tdo jtag i/o lines tricore cpu brkin brkout tp[15:0] (TC1765t only) ocdse fpi bus ocds/tcu dm a controller 16 16 16 trace
TC1765 data sheet 50 v1.2, 2002-12 preliminary clock generation unit the clock generation unit (cgu) in the TC1765, shown in figure 16 , consists of an oscillator circuit and a phase-locked loop (pll). the pll can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. the pll also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. it can execute emergency actions if it looses its lock on the external clock. in general, the cgu is controlled through the system control unit (scu) module of the TC1765. figure 16 clock generation unit block diagram mca04974 o scillator circuit xtal1 xtal2 & f osc phase detect. vco n divider pll f vco f sys system_ clk lock detector osc_ok deep sleep bypass 1 0 mux clock generation unit cgu system control unit scu k divider register pll_clc kdiv lock pllbyp
TC1765 data sheet 51 v1.2, 2002-12 preliminary pll operation the f vco clock of the pll has a frequency which is a multiple of the externally applied clock f osc . the factor for this is controlled through the fix divider value n (n = 10) applied to the divider in the feedback path. the k-divider is defined by bit field kdiv. table 6 lists the possible values for kdiv and the resulting division factor. the vco output frequency and the resulting system clock is determined by: table 6 output frequencies f sys derived from various output factors k-factor f sys duty cycle [%] selected factor kdiv f vco = 150 mhz f vco = 160 mhz f vco = 200 mhz 2 000 b 75 1) 1) these combinations cannot be used because the maximum system clock of 40 mhz is exceeded. 80 1) 100 1) 50 4 010 b 37.5 40 50 1) 50 5 2) 2) these odd k-factors should not be used (not tested because of the unsymmetrical duty cycle). 011 b 30 32 40 40 6 100 b 24.5 26.67 33.33 50 8 101 b 18.75 20 25 50 9 2) 110 b 16.67 17.78 22.22 44 10 111 b 15 16 20 50 16 001 b 9.38 10 12.5 50 f vco = 10 f osc f sys = f vco / k = f osc 10 k
TC1765 data sheet 52 v1.2, 2002-12 preliminary recommended oscillator circuits the oscillator circuit, designed to work with both, an external crystal oscillator or an external stable clock source, basically consists of an inverting amplifier with xtal1 as input and xtal2 as output. when using a crystal, a proper external oscillator circuitry must be used, connected to both pins, xtal1 and xtal2. the on-chip oscillator frequency can be within the range of 4 mhz to 16 mhz. when using an external clock signal it must be connected to xtal1. xtal2 is left open (unconnected). for direct drive operation without pll, the frequency of an external clock must not exceed 40 mhz. figure 17 shows the recommended external oscillator circuitries for both operating modes, external crystal mode and external input clock mode. figure 17 oscillator circuitries for the oscillator of the TC1765 the following external passive components are recommended: ? crystal: max. 16 mhz ? c 1 , c 2 : 10 pf a block capacitor between v ddosc and v ssosc is recommended, too. ? c 1 , c 2 : 12 pf note: for crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. mcb04996 TC1765 oscillator v ddosc v ssosc c 1 4-16 mhz c 2 xtal1 xtal2 TC1765 oscillator v ddosc v ssosc xtal1 xtal2 external clock signal
TC1765 data sheet 53 v1.2, 2002-12 preliminary power supply figure 18 shows the TC1765?s power supply concept, where certain logic modules are individually supplied with power. this concept improves the emi behavior by reduction of the noise cross coupling. also the operation margin is improved in sensitive modules like the a/d converter by noise reduction. figure 18 TC1765 power supply concept TC1765 mcd05227 cpu & control & peripherals ebu, tp v ddp (3.3 - 5 v) v ss v ddsbram (2.5 v) v ss v ddram (2.5 v) v ss adc0 control logic adc1 control logic v dda0 (2.5 v) v ssa0 v ddm (5 v) v ssm v dda1 (2.5 v) v ssa1 dmu pmu gpio ports (p0-p5) & dedicated pins v dd (2.5 v) v ss v ddosc (2.5 v) v ssosc osc
TC1765 data sheet 54 v1.2, 2002-12 preliminary ports power supply the TC1765?s port power supply concept is shown in figure 19 . the external bus unit (ebu) i/o lines are in the core and ebu v dd power supply group for 2.5 v nominal operating voltage. the general purpose input/outputs (gpios) provide 3.3 to 5 v nominal voltage input/output acceptance and drive characteristics. figure 19 ports power supply concept power-up sequence during power-up the reset pin porst has to be held active until both power supply voltages have reached at least their minimum values. during the power-up time (rising of the supply voltages from 0 to their regular operating values) it has to be ensured, that the difference between v ddp and v dd never drops below -0.5 v. power loss if v ddp is dropping below v dd , external circuitry in the power supply has to ensure, that v dd is also limited to the same level. if v ddi is dropping below the operating range, v ddp may stay active. powering down during powering down (falling of the supply voltages from their regular operating values to zero), it has to be ensured, that the difference between v ddp and v dd never drops below -0.5 v. mca05226 v ss ebu i/o lines (pads) & schmitt trigger ports 0 to 5 (pads) & schmitt trigger v dd (2.5 v) v ddp (3.3 - 5 v) port logic
TC1765 data sheet 55 v1.2, 2002-12 preliminary identification register values table 7 TC1765 identification registers short name address value pmu_id c7ff ff08 h 0006 c003 h dmu_id d7ff ff08 h 0007 c003 h scu_id f000 0008 h 0003 c003 h manid f000 0070 h 0000 1820 h chipid f000 0074 h 0000 8601 h rtid f000 0078 h 0000 0000 h bcu_id f000 0208 h 0000 6a05 h stm_id f000 0308 h 0000 c002 h jpd_id f000 0408 h 0000 6301 h ebu_id f000 0508 h 0005 c004 h gptu_id f000 0708 h 0001 c002 h asc0_id f000 0808 h 0000 4401 h asc1_id f000 0908 h 0000 4401 h ssc0_id f000 0a08 h 0000 4525 h ssc1_id f000 0b08 h 0000 4525 h gpta_id f000 1808 h 0002 c002 h adc0_id f000 2208 h 0000 3103 h dma_id f000 3f08 h 0018 c001 h can_id f010 0008 h 0000 4110 h cpu_id fffe ff08 h 0000 0202 h
TC1765 data sheet 56 v1.2, 2002-12 preliminary parameter interpretation the parameters listed on the following pages partly represent the characteristics of the TC1765 and partly its demands on the system. to aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ?symbol?: cc ( c ontroller c haracteristics): the logic of the TC1765 will provide signals with the respective timing characteristics. sr ( s ystem r equirement): the external system must provide signals with the respective timing characteristics to the TC1765. pin classes the TC1765 has three classes of digital i/o pins: ? class a pins, which are 3.0 to 5.25 v voltage pins ? class b pins, which are 2.5 v nominal voltage pins (input tolerant for 3.3 v) ? class c pins, which are 2.5 v nominal voltage pins only table 8 shows the assignments of all digital i/o pins to pin classes and to v dd power supply pins. table 8 assignments of digital pins to pin classes and power supply pins pins pin classes power supply port 0 to port 5, bypass, hdrst class a (3.0 to 5.25 v) v ddp v ss d[31:0], a[23:0], cs[3:0] , csemu /csovl , bc[3:0] , rd , rd/wr , adv, wait /ind , baa , code , trst , tck, tdi, tdo, tms, odcse , brkin , brkout , nmi , porst , ecout, ecin, cpuclk, testmode , tp[15:0] class b (nominal 2.5 v) v dd xtal1, xtal2 class c (nominal 2.5 v) v ddosc v ssosc no pins assigned (nominal 2.5 v) v ddram v ddsbram v ss
TC1765 data sheet 57 v1.2, 2002-12 preliminary absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. parameter symbol limit values unit notes min. max. ambient temperature t a -40 125 c under bias storage temperature t a -65 150 c? junction temperature t j ?150 c under bias voltage on v ddp with respect to v ss v dd -0.5 6.2 v see table 8 voltage on v dd , v ddosc , v ddram and v ddsbram with respect to v ss v dd -0.5 3.25 v ? voltage on any class a input pin with respect to v ss v in -0.5 v dd + 0.5 v ? voltage on any class b input pin with respect to v ss v in -0.5 3.7 v ? voltage on any class c input pin with respect to v ss v in -0.5 v ddosc + 0.5 v? input current on any pin during overload condition i in -10 10 ma ? absolute sum of all input currents during overload condition i in ? |100| ma ?
TC1765 data sheet 58 v1.2, 2002-12 preliminary package parameters (p-lbga-260) operating conditions the following operating conditions must not be exceeded in order to ensure correct operation of the TC1765. all parameters specified in the following table refer to these operating conditions, unless otherwise noticed. parameter symbol limit values unit notes min. max. power dissipation p diss ?0.9w? thermal resistance r tha ? 24.8 k/w chip to ambient parameter symbol limit values unit notes min. max. digital supply voltage 1) v ddp 3.0 5.25 2) vclass a pins v dd v ddosc v ddram 2.3 2.75 3) v class b and class c pins 4) v ddsbram 2.25 2.75 v 4)5) digital ground voltage v ss 0v? ambient temperature under bias t a -40 +125 c? analog supply voltages v dda 2.25 2.75 v ? v ddm 4.5 5.25 v ? analog reference voltage v aref 4 v ddm + 0.05 v 6) analog ground voltage v agnd v ssa - 0.05 v ssa + 0.05 v 7) analog input voltage v ain v agnd v aref v? cpu clock f sys ?40mhz? overload current i ov -10 10 ma 8)9)10) short circuit current i sc -10 10 ma 5)6)11) absolute sum of overload + short circuit currents | i ov | + | i sc | ?|50|ma 9) external load capacitance c l ?50pf?
TC1765 data sheet 59 v1.2, 2002-12 preliminary 1) digital supply voltages applied to the TC1765 must be static regulated voltages which allow a typical voltage swing of 10%. 2) voltage overshoot to 6.5 v is permissible, provided that the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 hour. 3) voltage overshoot to 4 v is permissible, provided that the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 hour. 4) in order to minimize the danger of latch-up conditions, these 2.5 v v dd power supply pins should be kept at the same voltage level during normal operating mode. this condition is typically achieved by generating the 2.5 v power supplies from a single voltage source. the condition is also valid in normal operating mode if a separate stand-by power supply v ddsbram is used. 5) the minimum voltage at pin v ddsbram during TC1765 power down mode is 1.8 v in order to keep the contents of sbram valid. the core power supply v dd must be below the standby power supply v dd < v ddsbram + 0.3 v. 6) the value of v aref is permitted to be within the range of v ssa - 0.05 v < v aref < v ddm + 0.05 v. the value specified for the total unadjusted error (tue) is not guaranteed while the v aref is out of the specified range. 7) the value of v agnd is permitted to be within the range of v ssa - 0.05 v < v agnd < v ddm + 0.05 v. the value specified for the total unadjusted error (tue) is not guaranteed while the v agnd is out of the specified range. 8) overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. v ov > v dd + 0.5 v or v ov < v ss - 0.5 v). the absolute sum of input overload currents on all port pins may not exceed 50 ma . the supply voltage must remain within the specified limits. 9) not 100% tested, guaranteed by design and characterization. 10) applicable for analog inputs. 11) applicable for digital inputs.
TC1765 data sheet 60 v1.2, 2002-12 preliminary dc characteristics input/output dc-characteristics v ss = 0 v; t a = -40 c to +125 c; parameter 1) symbol limit values unit test conditions min. max. class a pins ( v ddp = 3.0 to 5.25 v) output low voltage 2) v ol cc ? 0.45 v i ol = 2.4 ma 3) i ol = 600 a 4) v ddp = 4.5 to 5.25 v 0.2 v ddp v i ol = 2.4 ma i ol = 600 a 4) v ddp = 3.0 to 4.49 v output high voltage 2) v oh cc 0.7 v ddp ?v i oh = -2.4 ma i oh = -600 a 4) v ddp = 4.5 to 5.25 v v i oh = -2.4 ma i oh = -600 a 4) v ddp = 3.0 to 4.49 v input low voltage 5) v il sr -0.5 0.8 v v ddp = 4.5 to 5.25 v (ttl) 0.45 v ddp v v ddp = 4.5 to 5.25 v (cmos) 0.2 v ddp v v ddp = 3.0 to 4.49 v (cmos) input high voltage 5) v ih sr 2.0 v ddp +0.5 v v ddp = 4.5 to 5.25 v (ttl) 0.73 v ddp v v ddp = 3.0 to 5.25 v (cmos) pull-up current 6)7) | i puh | cc ? 10 a v out = v ddp - 0.02 v | i pul | cc 120 600 a v out = 0.5 v ddp pull-down current 8)7) | i pdl | cc ? 10 a v out = 0.02 v | i pdh | cc 120 700 a v out = 0.5 v ddp
TC1765 data sheet 61 v1.2, 2002-12 preliminary class b pins ( v ddp05 = 2.30 to 2.75 v) output low voltage v ol cc ? 0.2 v dd v i ol = 2.4 ma 0.45 v i ol = 600 a output high voltage v oh cc 0.7 v dd ?v i oh = -2.4 ma 0.9 v dd ?v i oh = -600 a input high voltage v ih sr 0.7 v dd 3.7 v ? input low voltage v il sr -0.5 0.2 v dd v? pull-up current 6)7) | i puh | cc ? 10 a v out = v dd - 0.02 v | i pul | cc 50 250 a v out = 0.5 v dd pull-down current 8)7) | i pdl | cc ? 10 a v out = 0.02 v | i pdh | cc 40 300 a v out = 0.5 v dd class a and b pins input hysteresis hys cc 0.030 v ddx 9) ?vcmos only 10) v ddx limits see 11) input leakage current (digital i/o) i oz2 cc ? 500 na 0 v < v in < v ddx 9) peak short-circuit current peak back-drive current (per digital pin) peak time & period time 12)13) i scbdpeak sr ? 20 ma 14)10) constant short-circuit current constant back-drive current (per digital pin) i scbdcons sr ? 10 ma 14)10) input/output dc-characteristics (cont?d) v ss = 0 v; t a = -40 c to +125 c; parameter 1) symbol limit values unit test conditions min. max.
TC1765 data sheet 62 v1.2, 2002-12 preliminary pin capacitance 10) (digital i/o) c io cc ? 10 pf f = 1 mhz t a = 25 c class c pins ( v ddosc = 2.30 to 2.75 v), see page 68 1) all class a pins of the TC1765 are equipped with low-noise output drivers, which significantly improve the device?s emi performance. these low-noise drivers deliver their maximum current only until the respective target output level is reached. after that the output current is reduced. this results in an increased impedance of the driver, which attenuates electrical noise from the connected pcb tracks. the current, which is specified in column ?test conditions?, is delivered in any case. 2) this specification is not valid for outputs of gpio lines, which are switched to open drain mode. in open drain mode the output will float and the voltage results from the external circuitry. 3) output drivers in high current mode. 4) condition for output driver in dynamic current mode & low current mode ? guaranteed by design characterization. 5) input characteristics can be switched between ttl and cmos via register px_picon except for dedicated pins which have cmos input characteristics. 6) the maximum current can be drawn while the respective signal line remains inactive. 7) the two pull-up/pull-down current test conditions for v out cover the curves as shown in figure 20 and figure 21 . all pull-up/pull-down currents are given as absolute values. 8) the minimum current must be drawn in order to drive the respective signal line active. 9) in case of class b pins v ddx = v dd . in case of class a pins v ddx = v ddp . 10) guaranteed by design characterization. 11) the test condition for class a pins is: v ddp = 4.5 to 5.25 v; for class b pins: v dd = 2.3 to 2.75 v; 12) the max. peak-short-circuit current resp. max. peak-back-drive current is limited by max. 20 ma and the peak period equivalent of 10 ma constant-short-circuit current resp. 10 ma constant-back-drive current. the integral of i scbdpeak over the peak period is thus limited to 10 ma (provided: i scbdpeak 20 ma). 13) to be defined for class b pads. 14) short-circuit or back-drive conditions during operation occur if the voltage on the respective pin exceeds the specified operating range (i.e. v scbd > v ddp + 0.5 v or v scbd < v ss - 0.5 v ) or a short circuit condition occurs on the respective pin. the absolute sum of input i scbd and i ov currents on all port pins must not exceed 100 ma at any time. the supply voltage ( v ddp and v ss ) must remain within the specified limits. under short- circuit conditions the corresponding pin is not ready for use. in case of class b pins v ddx = v dd . in case of class a pins v ddx = v ddp . input/output dc-characteristics (cont?d) v ss = 0 v; t a = -40 c to +125 c; parameter 1) symbol limit values unit test conditions min. max.
TC1765 data sheet 63 v1.2, 2002-12 preliminary pull-up/pull-down characteristics figure 20 pull-up/pull-down characteristics of class a pins mcd05139 0 0 a i v v 12 34 56 pull-up 0 0 a i v v 12 34 56 pull-down best case nominal 100 200 300 400 500 600 700 100 200 300 400 500 600 700 worst case nominal best case worst case
TC1765 data sheet 64 v1.2, 2002-12 preliminary figure 21 pull-up/pull-down characteristics of class b pins note: the pull-up/pull-down characteristics as shown in figure 20 and figure 21 are guaranteed by design characterization. mcd05140 0 0 50 100 150 200 250 a i v v 0.5 1 1.5 2 2.5 3 pull-up 0 0 50 100 150 200 250 a i v v 0.5 1 1.5 2 2.5 3 pull-down best case nominal worst case worst case nominal best case
TC1765 data sheet 65 v1.2, 2002-12 preliminary ad converter characteristics v ss = 0 v; t a = -40 c to +125 c; parameter symbol limit values unit test conditions min. typ. max. analog supply voltages v ddax sr 2.25 2.5 2.75 v 1) v ddm sr 4.5 5 5.25 v ? analog ground voltage v ssax sr -0.1 ? 0.1 v 1) analog reference voltage v arefx sr 4 ? v ddm + 0.05 v 1)2) analog reference ground v agndx sr v ssax - 0.05 ? v ssax + 0.05 v 1)3) analog input voltage range v ain sr v agndx ? v arefx v 1) internal adc clock f ana 0.5 ? 5 mhz ? power-up calibration time t puc cc ? ? 3328 (3 + con.cps) t bc s? sample time t s cc (3 + con.cps) (chconn.stc + 2) t bc s 4) 6 t bc ?? s conversion time t c cc t s + (30 + con.cps 4) t bc + 2 t div s for 8-bit conv. 4) t s + (36 + con.cps 4) t bc + 2 t div s for 10-bit conv. 4) t s + (42 + con.cps 4) t bc + 2 t div s for 12-bit conv. 4) total unadjusted error tue 5) cc ? ? 1 lsb for 8-bit conv. ?? 2 lsb for 10-bit conv. ?? 6 lsb for 12-bit conv. overload current 6) i aov1 7) cc -2 ? +5 ma ? -2 0 ma k a =1.0 10 -3 0+5ma k a =1.0 10 -4 i aov2 8) cc -4 ? +10 ma ? -4 0 ma k a =1.0 10 -3 0+10ma k a =1.0 10 -4 overload coupling factor 9) k a cc ? ? 1.0 10 -3 ? see i aov1 and i aov2 1.0 10 -4 ?
TC1765 data sheet 66 v1.2, 2002-12 preliminary input leakage current at analog inputs i oz1 cc ? ? 200 na 0 v< v in < v dda 1) input leakage current at v agnd and v aref i oz2 cc ? ? 500 na 0 v< v in < v dda 1) switched cap. at positive reference voltage input c arefsw cc ?1520 pf 10) switched cap. at negative reference voltage input c agndsw cc ?1520 pf 10) total capacitance at analog voltage input c aintot cc ?1215 pf? switched cap. at analog voltage input c ainsw cc ? ? 10 pf 11) on resistance of the transmission gates in the analog voltage path r ain cc ? ? 0.7 k ? ? 1) suffix x = 0 refers to adc0 and suffix x = 1 refers to adc1. 2) the value of v aref is permitted to be within the range of v ssa - 0.05 v < v aref < v ddm + 0.05 v. the value specified for the total unadjusted error (tue) is not guaranteed while the v aref is out of the specified range. 3) the value of v agnd is permitted to be within the range of v ssa - 0.05 v < v agnd < v ddm + 0.05 v. the value specified for the total unadjusted error (tue) is not guaranteed while the v agnd is out of the specified range. 4) definitions for cps, stc, t bc and t div see figure 23 . 5) tue is tested at v aref = 5 v, v agnd = 0 v and v ddm = 4.9 v. 6) analog overload conditions during operation occur if the voltage on the respective adc pin exceeds the specified operating range (i.e. v aov > v ddm + 0.5 v or v aov < v ssm - 0.5 v ) or a short circuit condition occurs on the respective adc pin. the absolute sum of input currents on all port pins must not exceed 10 ma at any time. the supply voltage ( v dd , v dda0 , v dda1 and v ss , v ssa0 , v ssa1 ) must remain within the specified limits. under short-circuit conditions the corresponding pin is not ready for use. 7) applies for one analog input pin. 8) applies for two numeric adjacent analog input pins. ad converter characteristics (cont?d) v ss = 0 v; t a = -40 c to +125 c; parameter symbol limit values unit test conditions min. typ. max.
TC1765 data sheet 67 v1.2, 2002-12 preliminary figure 22 equivalent circuitry of analog input note: this equivalent circuitry for an analog input is also valid for the reference inputs v aref and v agnd . 9) the overload coupling factor ( k a ) defines the worst case relation of an overload condition ( i ov ) at one pin to the resulting leakage current ( i leak ) into an adjacent pin: | i leak | = k a | i ov |. thus under overload conditions an additional error leakage voltage ( v ael ) will be induced onto an adjacent analog input pin due to the resistance of the analog input source ( r ain ). that means v ael = r ain | i leak |. see also section 7.1.6 ?error through overload conditions? in the TC1765 peripheral units user?s manual for further explanations. 10) this represents an equivalent switched capacitance. this capacitance is not switched to the reference voltage at once. instead of this smaller capacitances are successively switched to the reference voltage. alternatively, the redistributed charge could be specified. 11) the switched capacitance at the analog voltage input must be charged within the sampling time. alternatively, the redistributed charge could be specified. mcs04879 r ain, source = v ain c ain, block r ain, on c aintot - c ainsw c ainsw a/d converter
TC1765 data sheet 68 v1.2, 2002-12 preliminary figure 23 adc clock circuit note: the frequency of f adc is the system clock frequency ( f sys ) divided by the value of bit field adcx_clc.rmc. oscillator pins (class c pins) t a = -40 c to +125 c; v ddosc = 2.30 to 2.75 v; v ssosc = 0 v; parameter symbol limit values unit test conditions min. max. input low voltage at xtal1 v ilx sr -0.5 0.3 v ddosc v? input high voltage at xtal1 v ihx rr 0.7 v ddosc v ddosc +0.5 v? input current at xtal1 i ix1 cc ? 20 a0 v < v in < v ddosc input leakage current xtal1 1) 1) only applicable in deep sleep mode. i oz cc ? 200 na 0 v < v in < v ddosc mca04657 programmable clock divider (1:1) to (1:128) 4:1 3:1 f bc f div peripheral clock divider (1:1) to (1:8) f adc f ana programmable counter sample time t s con.pcd con.ctc con.cps chconn.stc f timer control/status logic interrupt logic external trigger logic external multiplexer logic request generation logic a/d converter module arbiter (1:20) control unit (timer)
TC1765 data sheet 69 v1.2, 2002-12 preliminary power supply current t a = -40 c to +125 c; parameter symbol limit values unit test conditions min. typ. 1) 1) parameters in this column are tested at 25 c, 40 mhz system clock (if applicable) and nominal v dd voltages. max. active mode supply current i dd cc ? ? 200 ma porst = v il 2)3) 2) these parameters are tested at v ddmax and 40 mhz system clock (bypass mode) with all outputs disconnected and all inputs at v il or v ih . 3) these power supply currents are defined as the sum of all currents at the v dd power supply lines: v dd + v ddp + v ddram + v ddsbram + v ddosc + v ddm + v dda0 + v dda1 ? 260 290 ma sum of i dds 4)3) 4) these power consumption characteristics are measured while running a typical application pattern. the power consumption of modules can increase or decrease using other application programs. the pll is inactive during this measurement. ?7 10ma i dd at v ddp 4) ?201? ma i dd at v dd (core and ebu) 4) ?31? ma i dd at v ddram 4) ?21 4) 120 5) 5) this parameter has been evaluated at design characterization using an atypical test pattern that makes extensive usage of the dmu memory. ma i dd at v ddsbram ?0.1? ma i dd at v ddax 4) idle mode supply current i id cc ? 123 ? ma porst = v ih 2)6)7) 6) all peripherals are enabled and in idle state. 7) guaranteed by design characterization. sleep mode supply current i sl cc ? 50 ? ma porst = v ih 2)7) deep sleep mode supply current i ds cc ? 5 900 aporst = v ih 8) 8) this is the sum of all 2.5 v power supply currents. ?1 4.4maporst = v ih 9) 9) this is the sum of all 5 v power supply currents. stand-by pin power supply current i sb cc ? 1 250 a i dd at v ddsbram 10) 10) TC1765 in deep sleep mode. ? 1 200 a 11) 11) all other v dd pins are at 0 v; t j = 150 c; v ddsbram = 2.0 v.
TC1765 data sheet 70 v1.2, 2002-12 preliminary ac characteristics output rise/fall times class a drivers (gpio ports 0 to 5): v ddp = 3.0 to 5.25 v; v ss = 0 v class b drivers (bus interface): v dd = 2.30 to 2.75 v; v ss = 0 v t a = -40 c to +125 c, unless otherwise noted; f sys = 40 mhz parameter symbol limit values unit test conditions min. typ. max. class a pins nominal output rise/ fall time 1) 1) measured from 10% output level to 90% output level and vice versa. t rfanom cc ?5?ns t a = 25 c, c l = 50 pf, v ddp = 5.0 v px_pocon.pdcy = 0 px_pocon.pecy = 0 maximal output rise/ fall time 1) t rfamax cc ??12ns c l = 50 pf px_pocon.pdcy = 0 px_pocon.pecy = 0 slow output rise/fall time 1) t rfaslow cc ??55ns c l = 100 pf px_pocon.pdcy = 0 px_pocon.pecy = 1 class b pins output rise/fall time 1) t rfbmax cc ??4nsfor ecout c l = 50 pf ? ? 7 ns for all class b pins except ecout c l = 50 pf
TC1765 data sheet 71 v1.2, 2002-12 preliminary testing waveforms t a = -40 c to +125 c; frequency: max. 40 mhz; class a pins: v ddp813 = 3.0 to 5.25 v; v ss = 0 v; figure 24 testing waveforms for class a pins class b and class c pins: v dd = 2.30 to 2.75 v; v ss = 0 v; v ddosc = 2.30 to 2.75 v; v ssosc = 0 v; figure 25 testing waveforms for class b and class c pins figure 26 tri-state testing waveforms for class b pins mct04880 v ihmin v ilmax v ohmin v olmax v ohmin v olmax test points ac inputs during testing are driven with v ihmin for a logic 1 and v ilmax for a logic 0. timing measurements are made at v ohmin for a logic 1 and v olmax for a logic 0. input and output low/high max./min. voltages are defined at page 60 . mct04881 v ihmin v ilmax v dd / 2 test points v dd / 2 ac inputs during testing are driven with v ihmin for a logic 1 and v ilmax for a logic 0. timing measurements are made at v dd /2 for a logic 1 and for a logic 0. input low/high max./min. voltages are defined at page 61 and page 68 . mct05074 v load + 0.1 v v oh - 0.1 v timing reference points v load - 0.1 v v ol - 0.1 v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to float when a 100 mv change from the loaded v oh / v ol level occurs ( i oh / i ol = 15 ma).
TC1765 data sheet 72 v1.2, 2002-12 preliminary input clock timing v ddosc = 2.30 to 2.75 v; v ssosc = 0 v; t a = -40 c to +125 c; figure 27 input clock timing parameter symbol limit values unit min. max. oscillator clock frequency direct drive f osc sr (= 1/ t osc ) 416mhz with pll 10 16 mhz input clock frequency driving at xtal1 direct drive 1/ t oscdd sr ? 40 mhz with pll 10 30 mhz input clock high time t 1 sr 7 ? ns input clock low time t 2 sr 7 ? ns input clock rise time t 3 sr ? 4ns input clock fall time t 4 sr ? 4ns mct04882 0.5 v ddosc input clock at xtal1 t osc t 1 t 2 v ihx v ilx t 4 t 3
TC1765 data sheet 73 v1.2, 2002-12 preliminary ecout and cpuclk timing v ss = 0 v; v dd = 2.30 to 2.75 v; t a = -40 c to +125 c; c l = 50 pf; figure 28 ecout/cpuclk output clock timing parameter symbol limit values unit min. typ. max. clock period t cpuclk t ecout cc 25 ?? ns clock high time t 5 cc 7.5 ?? ns clock low time t 6 cc 7.5 ?? ns clock rise time t 7 cc ?? 4ns clock fall time t 8 cc ?? 4ns clock duty cycle t 5 /( t 5 + t 6 ) dc cc 45 50 55 % 0.9 v dd mct05228 0.5 v ddp05 ecout cpuclk t clkout t 5 t 6 0.1 v dd t 8 t 7
TC1765 data sheet 74 v1.2, 2002-12 preliminary pll parameters note: all pll characteristics defined on this and the next page are guaranteed by design characterization. v ss = 0 v; v dd = 2.30 to 2.75 v; t a = -40 c to +125 c; phase locked loop operation when pll operation is enabled and configured (see figure 16 and page 51 ), the pll clock f vco (and with it the system clock f sys ) is constantly adjusted to the selected frequency. the relation between f vco and f sys is defined by: f vco =k f sys . the pll causes a jitter of f sys and cpuclk/ecout, which is directly derived from f sys and which has its frequency. the following two formulas define the (absolute) approximate maximum value of jitter d n in ns dependent on the k-factor, the system clock frequency f sys in mhz, and the number p of consecutive f sys periods. [1] [2] with rising number p of clock cycles the maximum jitter increases linearly up to a value of p that is defined by the k-factor of the pll. beyond this value of p the maximum accumulated jitter remains at a constant value. further, a lower system clock frequency f sys results in a higher maximum jitter. figure 29 gives an example for typical jitter curves with k =4@40mhz, k = 6 @33 mhz, and k = 8@20/25 mhz. parameter symbol limit values unit min. max. accumulated jitter d n see figure 29 ? vco frequency range f vco 150 200 mhz pll base frequency f pllbase 40 130 mhz pll lock-in time t l ? 200 s for p < 23.5 k d n [ns] = 3.9 f sys [mhz] p + 1.2 for p > 23.5 k d n [ns] = 91.7 f sys [mhz] k + 1.2
TC1765 data sheet 75 v1.2, 2002-12 preliminary figure 29 approximated maximum accumulated pll jitter for typical system clock frequencies f sys note: for safe clock generation and pll operation the definitions and restrictions as defined at pages 50 , 51 , and 72 must be regarded. mcd05141_mod 0 1.0 p ns d n 1.2 1.4 1.6 2.0 12 34 56 1.8 7 d n p k = m ax. jitter = number of consecutive f sys periods = k-divider of pll f sys = 20 mhz ( k = 8) f sys = 25 mhz ( k = 8) f sys = 33 mhz ( k = 6) f sys = 40 mhz ( k = 4)
TC1765 data sheet 76 v1.2, 2002-12 preliminary ebu demultiplexed timing v ss = 0 v; v dd = 2.30 to 2.75 v; t a = -40 c to +125 c; c l = 50 pf; parameter symbol limit values unit min. max. output delay from ecout t 10 cc 0 9 ns output delay from ecout t 11 cc -2 4 ns data setup to ecout t 12 sr 9 ? ns data hold from ecout 1) 1) valid for ebu_busconx.26 = 0. t 13 sr 1 ? ns data valid after ecout 1) t 15 cc 2 ? ns data setup to ecin 2) 2) valid for ebu_busconx.26 = 1 (early sample feature). t 31 sr see page 80 ? ns data hold from ecin 2) t 32 sr see page 80 ? ns
TC1765 data sheet 77 v1.2, 2002-12 preliminary figure 30 ebu demultiplexed read timing note: wait timing see figure 32 . address valid data valid mct05229 ecin adv rd rd/wr d[31:0] normal sampling bc[3:0] t 10 t 11 t 11 t 10 t 12 t 13 t 11 t 10 t 11 t 10 t 11 t 11 t 10 a[23:0] svm code csx data valid t 31 t 32 d[31:0] early sampling ecout
TC1765 data sheet 78 v1.2, 2002-12 preliminary figure 31 ebu demultiplexed write timing data valid mct05230 ecout adv csx rd rd/wr d[31:0] bc[3:0] t 10 t 11 t 11 t 10 t 11 t 10 t 11 t 10 t 11 t 11 t 10 t 15 t 10 address valid 1) code remains at high level during a demultiplexed write cycle a[23:0] code 1) svm
TC1765 data sheet 79 v1.2, 2002-12 preliminary wait timing (fpi bus to external memory) v ss = 0 v; v dd = 2.30 to 2.75 v; t a = -40 c to +125 c; c l = 50 pf; figure 32 wait timing (from fpi bus to external memory) parameter symbol limit values unit min. max. wait setup to ecout t 50 sr 14 1) 1) guaranteed by design characterization. ? ns wait hold from ecout t 51 sr 14 1) ? ns wait setup to ecout t 52 sr 11 ? ns wait hold from ecout t 53 sr 2 ? ns mct05231 ecout t 50 t 51 t 50 t 51 wait synchronous mode ecout t 52 t 53 t 52 t 53 wait asynchronous mode
TC1765 data sheet 80 v1.2, 2002-12 preliminary ebu burst mode timing v ss = 0 v, v dd = 2.30 to 2.75 v; t a = -40 c to +125 c; c l = 50 pf; figure 33 burst mode timing (instruction read) parameter symbol limit values unit min. max. output delay from ecin t 30 cc 2 14 ns data setup to ecin t 31 sr 4 1) 1) guaranteed by design characterization. ? ns data hold from ecin t 32 sr 1 1) ? ns address valid valid valid mct05232 ecin t 30 t 30 t 30 t 30 t 30 t 30 t 30 t 32 t 31 t 32 t 31 a[23:2] cs0 code rd baa adv d[31:0] note: wait must be 1 during a burst mode read cycle. t 30 t 30
TC1765 data sheet 81 v1.2, 2002-12 preliminary trace port timing (TC1765t only) this timing is applicable for tp[15:0] when cpu or dma trace mode is enabled (scu_con.eten = 1). v ss = 0 v; v dd = 2.30 to 2.75 v; t a = -40 c to +125 c; c l = 50 pf; figure 34 trace port timing parameter symbol limit values unit min. max. tp[15:0] and brkout high/low from cpuclk t 55 cc 0 8 ns mct05233 cpuclk t 55 tp[15:0] brkout old state new state
TC1765 data sheet 82 v1.2, 2002-12 preliminary ssc master mode timing v ss = 0 v; v ddp = 4.5 to 5.25 v; t a = -40 c to +125 c; c l = 50 pf; figure 35 ssc master mode timing parameter symbol limit values unit min. max. sclk / mtsr low/high from ecout 1) 1) this parameter is valid for high current mode output driver characteristic and normal timing edge characteristic (pocon.pecx = 0 and pocon.pdcx = 0) of the corresponding ssc output lines. t 60 cc ? 7ns mrst setup to slck rising/falling edge t 61 sr 18 2) 2) guaranteed by design characterization. ? ns mrst hold from slck rising/falling edge t 62 sr 10 2) ? ns state n mct05234 ecout sclk t 60 mtsr t 60 t 61 t 62 data valid state n-1 state n+1 t ecout t 60 mrst note: the timing diagram assumes the highest possible baudrate operation. ( f ssc = f ecout , sscx_clc.rmc = 1, sscx_br.br_value = 0000 h )
TC1765 data sheet 83 v1.2, 2002-12 preliminary package outlines p-lbga-260-2 plastic low profile pitch ball grid array gpa09421 you can find all of our packages, sorts of packing and others in our infineon internet page ? products ? : http://www.infineon.com/products. dimensions in mm smd = surface mounted device
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